The detection of defects on wafers is of particular interest to the semiconductor industry. In many instances, a defect in a wafer, if uncorrected, can cause the failure of the final product, an integrated circuit (IC) chip. Identifying the defect during processing is particularly valuable for several reasons. For example, if the defects were discovered during one step of the processing, it is possible that the wafer could be reworked to eliminate the defect(s). Additionally, even if the wafer could not be reworked, identifying the location and frequency of the defects will provide important information regarding the repeatability and quality of the previous processes. This information can then be used to makes changes to the previous processes so as to minimize the defects.
Not only is location and frequency important data to collect regarding defects, the characterization of the defects is also important. After determining what defects are present, it can be determined how that particular defect was created. For example, chemical metal planarization (CMP) causes many types of defects. These defects include surface defects, embedded defects, and microscratches. Surface defects can be the result of residual material, which can include material from the polishing pad, slurry, residual tungsten, titanium or titanium oxide. Therefore, by characterizing the defect after a particular process, for example CMP, it can be determined how the defect was created.
A particularly serious defect is an embedded particle in an oxide that the CMP process rips out thereby leaving a void in the oxide. This void could subsequently be filled with tungsten or another metal and not removed by a later CMP process. This puddle of metal could then result in a die-killing short circuit at subsequent metal levels.
Other types of defects exist during the processing of semiconductor wafers. Common defects are unfilled vias or windows and deviations in the via top profile. Unfilled vias have many causes including the metal being pulled out during the CMP process or the filling of the via may have been blocked by a particle. Deviations in the via top profile can be caused due to local arcing or cratering.
Two types of equipment are commonly used to locate these types of defects. The typical procedure is to inspect the wafer for defects with an optical comparitor tool. Once the locations of defects are determined, the locations are given to another tool, which will characterize the defect. Two such tools used for characterization of defects are an optical inspection tool or a scanning electron microscope (SEM). The advantage of using an optical inspection tool is its ability to position itself to the defect and quickly focus on the defect. However, an optical inspection tool has difficulty distinguishing between a surface defect and a void at high magnification levels of approximately 0.25 micros per pixel. As the features become smaller than 0.25 microns, the wavelength of the light reflected from defects of similar size is not long enough for the optical inspection tool to characterize the defect.
Alternatively, the defects can be characterized using a SEM. However, use of a SEM presents different problems. A SEM cannot easily focus on a substantially flat oxide film. Also, throughput (i.e., the number of inspections during a given period of time) of an SEM is much smaller than the throughput of an optical inspection tool. With the throughput of an SEM being so low, the use of a SEM during manufacturing is typically considered not feasible. Thus, as the size of features becomes smaller and the size of defects to be detected also becomes smaller, the current devices and methods of detecting these defects are inadequate.
Another problem associate with current inspection methods are their vulnerability to "noise". One type of noise that affects current inspection methods is from the underlying metal pattern or from the metal grain in the situation of large metal areas. Another type of noise is color noise originating from the variation of oxide film thickness across the wafer and from die to die.